View NCP561-D_2922535.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2002 may, 2002 rev. 3 1 publication order number: ncp561/d ncp561 150 ma cmos low iq low-dropout voltage regulator the ncp561 series of fixed output low dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. the ncp561 series features an ultralow quiescent current of 3.0 a. each device contains a voltage reference unit, an error amplifier, a pmos power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. the ncp561 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 1.0 f. the device is housed in the microminiature tsop5 surface mount package. standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3 and 5.0 v. features ? low quiescent current of 3.0 a typical ? low dropout voltage of 170 mv at 150 ma ? low output voltage option ? output voltage accuracy of 2.0% ? industrial temperature range of 40 c to 85 c typical applications ? battery powered instruments ? handheld instruments ? camcorders and cameras driver w/ current limit v in v out thermal shutdown enable gnd off on 1 3 5 2 figure 1. representative block diagram this device contains 28 active transistors see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information tsop5 (sot235, sc595) sn suffix case 483 1 5 pin connections and marking diagram 1 3 n/c v in 2 gnd enable 4 v out 5 xxxyw xxx = version y = year w = work week (top view) http://onsemi.com
ncp561 http://onsemi.com 2 pin function description pin no. pin name description 1 vin positive power supply input voltage. 2 gnd power supply ground. 3 enable this input is used to place the device into lowpower standby. when this input is pulled low, the device is disabled. if this function is not used, enable should be connected to vin. 4 n/c no internal connection. 5 v out regulated output voltage. maximum ratings rating symbol value unit input voltage v in 6.0 v enable voltage enable 0.3 to v in +0.3 v output voltage v out 0.3 to v in +0.3 v power dissipation and thermal characteristics power dissipation thermal resistance, junction to ambient p d r ja internally limited 250 w c/w operating junction temperature t j +125 c operating ambient temperature t a 40 to +85 c storage temperature t stg 55 to +150 c 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per milstd883, method 3015 machine model method 200 v 2. latch up capability (85 c) 100 ma dc with trigger voltage.
ncp561 http://onsemi.com 3 electrical characteristics (v in = v out(nom.) + 1.0 v, v enable = v in , c in = 1.0 f, c out = 1.0 f, t j = 25 c, unless otherwise noted.) characteristic symbol min typ max unit output voltage (t a = 25 c, i out = 1.0 ma) 1.5 v 1.8 v 2.5 v 2.7 v 2.8 v 3.0 v 3.3 v 5.0 v v out 1.455 1.746 2.425 2.646 2.744 2.940 2.234 4.90 1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0 1.545 1.854 2.575 2.754 2.856 3.060 3.366 5.10 v line regulation 1.5 v4.4 v (v in = v o(nom.) + 1.0 v to 6.0 v) 4.5 v5.0 v (v in = 5.5 v to 6.0 v) reg line 10 10 20 20 mv load regulation (i out = 10 ma to 150 ma) reg load 30 60 mv output current (v out = (v out at i out = 150 ma) 3.0%) 1.5 v to 3.9 v (v in = v o(nom.) + 2.0 v) 4.0 v to 5.0 v (v in = 6.0 v) i o(nom.) 150 150 ma dropout voltage (t a = 40 c to 85 c, i out = 150 ma, measured at v out 3.0%) 1.5 v 1.7 v 1.8 v 2.4 v 2.5 v 2.7 v 2.8 v 3.2 v 3.3 v 4.9 v 5.0 v v in v out 330 240 150 140 130 120 500 360 250 230 200 190 mv quiescent current (enable input = 0 v) (enable input = v in , i out = 1.0 ma to i o(nom.) ) i q 0.1 4.0 1.0 8.0 a output short circuit current 1.5 v to 3.9 v (v in = v o(nom.) + 2.0 v) 4.0 v to 5.0 v (v in = 6.0 v) i out(max) 160 160 400 400 800 800 ma output voltage noise (f = 20 hz to 100 khz, v out = 3.0, v i out = 1.0 v) v n 60 vrms enable input threshold voltage (voltage increasing, output turns on, logic high) (voltage decreasing, output turns off, logic low) v th(en) 1.3 0.2 v output voltage temperature coefficient t c 100 ppm/ c 3. maximum package power dissipation limits must be observed. pd t j(max) t a r ja 4. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
ncp561 http://onsemi.com 4 typical characteristics temperature (c ) v in v out , dropout voltage (mv) 0 20 40 60 80 100 120 140 160 180 50 25 0 25 50 75 100 125 temperature (c ) v out , output voltage (v) 2.975 2.980 2.985 2.990 2.995 3.000 3.005 3.010 3.015 50 0 50 10 0 figure 2. dropout voltage vs. temperature figure 3. output voltages vs. temperature v out = 3.0 v 150 ma load 100 ma load 50 ma load i out = 10 ma v in = 6.0 v v in = 4.0 v temperature (c ) i q , quiescent current ( a) 3.00 3.25 3.50 3.75 4.00 4.25 4.50 50 0 50 i out = 10 ma v in = 4.0 v figure 4. quiescent current vs. temperature 100 temperature (c ) i q , quiescent current ( a) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 05 v out = 3.0 v i out = 0 ma t a = 25 c figure 5. quiescent current vs. input voltage 1234 6 1.5 2.0 2.5 3.0 3.5 4.0 4.5 05 v out = 3.0 v i out = 50 ma t a = 25 c 1234 6 figure 6. ground current vs. input voltage v in , input voltage (v) i gnd , ground pin current ( a) 5.0 noise characterization output noise voltage ( v/ hz ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10 100 1 k 10 k 100 k 1000 k figure 7. output noise voltage 1.0 ma 150 ma 4.75
ncp561 http://onsemi.com 5 typical characteristics 250 200 150 100 50 0 0 50 100 150 0 200 400 600 800 1000 i out , output current (ma) change in output voltage (mv) time ( s) v in , input voltage (mv) 400 200 0 200 400 40 50 60 figure 8. line transient response figure 9. load transient response i out = 10 ma c out = 1.0 f 250 200 150 100 50 0 change in output voltage (mv) 0 50 100 150 0 200 400 600 800 1000 120 0 i out , output current (ma) change in output voltage (mv) time ( s) figure 10. load transient response 1200 v in = 4.0 v v out = 3.0 v c in = 1.0 f c out = 10 f tantalum 0 1 2 3 0 200 400 600 800 1000 v out , output voltage (v) enable voltage (v) time ( s) figure 11. turnon response 1200 c in = 1.0 f c out = 1.0 f i out = 10 ma 1400 160 0 0 2 4 0 0.5 1.0 1.5 012 3 v out , output voltage (v) v in , input voltage (v) figure 12. output voltage vs. input voltage 456 2.0 2.5 3.0 3.5 c in = 1.0 f c out = 1.0 f t a = 25 c v enable = v in v in = 4.0 v v out = 3.0 v c in = 1.0 f c out = 10 f al. elec. surface mount 0 0.2 0.4 0.8 1.0 1.2 1.4 time ( s) 0.6 1.6 1.8 2.0
ncp561 http://onsemi.com 6 definitions load regulation the change in output voltage for a change in output current at a constant temperature. dropout voltage the input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. measured when the output drops 3.0% below its nominal. the junction temperature, load current, and minimum input supply requirements affect the dropout level. maximum power dissipation the maximum total dissipation for which the regulator will operate within its specifications. quiescent current the quiescent current is the current which flows through the ground when the ldo operates without a load on its output: internal ic operation, bias, etc. when the ldo becomes loaded, this term is called the ground current. it is actually the difference between the input current (measured through the ldo input pin) and the output current. line regulation the change in output voltage for a change in input voltage. the measurement is made under conditions of low dissipation or by using pulse technique such that the average chip temperature is not significantly affected. line transient response typical over and undershoot response when input voltage is excited with a given slope. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated at typically 160 c, the regulator turns off. this feature is provided to prevent failures from accidental overheating. maximum package power dissipation the maximum power package dissipation is the power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125 c. depending on the ambient power dissipation and thus the maximum available output current.
ncp561 http://onsemi.com 7 applications information a typical application circuit for the ncp561 series is shown in figure 13. input decoupling (c1) a 1.0 f capacitor either ceramic or tantalum is recommended and should be connected close to the ncp561 package. higher values and lower esr will improve the overall line transient response. tdk capacitor: c2012x5r1c105k, or c1608x5r1a105k output decoupling (c2) the ncp561 is a stable regulator and does not require any specific equivalent series resistance (esr) or a minimum output current. capacitors exhibiting esrs ranging from a few m up to 3.0 can thus safely be used. the minimum decoupling value is 1.0 f and can be augmented to fulfill stringent load transient requirements. the regulator accepts ceramic chip capacitors as well as tantalum devices. larger values improve noise rejection and load regulation transient response. tdk capacitor: c2012x5r1c105k, or c1608x5r1a105k, or c3216x7r1c105k enable operation the enable pin will turn on the regulator when pulled high and turn off the regulator when pulled low. these limits of threshold are covered in the electrical specification section of this data sheet. if the enable is not used then the pin should be connected to v in . hints please be sure the vin and gnd lines are suf ficiently wide. when the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction. set external components, especially the output capacitor, as close as possible to the circuit, and make leads a short as possible. thermal as power across the ncp561 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material and also the ambient temperature effect the rate of temperature rise for the part. this is stating that when the ncp561 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power dissipation applications. the maximum dissipation the package can handle is given by: pd t j(max) t a r ja if junction temperature is not allowed above the maximum 125 c, then the ncp561 can dissipate up to 400 mw @ 25 c. the power dissipated by the ncp561 can be calculated from the following equation: p tot [ v in *i gnd (i out ) ] [ v in v out ] *i out or v inmax p tot v out * i out i gnd i out if a 150 ma output current is needed then the ground current from the data sheet is 4.0 a. for an ncp561sn30t1 (3.0 v), the maximum input voltage will then be 5.6 v. figure 13. typical application circuit v out battery or unregulated voltage c1 c2 off on 1 2 3 5 4 + +
ncp561 http://onsemi.com 8 output r 1 2 3 5 4 input 1.0 f 1.0 f output 1 2 3 5 4 input 1.0 f 1.0 f q2 q1 r3 r1 r2 output 1 2 3 5 4 input 1.0 f 1.0 f output 1 2 3 5 4 enable 1.0 f 1.0 f c output 1 2 3 5 4 input 1.0 f 1.0 f q1 r 5.6 v figure 14. current boost regulator figure 15. current boost regulator with short circuit limit figure 16. delayed turnon figure 17. input voltages greater than 6.0 v the ncp561 series can be current boosted with a pnp transis- tor. resistor r in conjunction with v be of the pnp determines when the pass transistor begins conducting; this circuit is not short circuit proof. input/output differential voltage minimum is increased by v be of the pass resistor. short circuit current limit is essentially set by the v be of q2 and r1. i sc = ((v beq2 ib * r2) / r1) + i o(max) regulator if a delayed turnon is needed during power up of several volt- ages then the above schematic can be used. resistor r, and capacitor c, will delay the turnon of the bottom regulator. a regulated output can be achieved with input voltages that exceed the 6.0 v maximum rating of the ncp561 series with the addition of a simple preregulator circuit. care must be taken to prevent q1 from overheating when the regulated output (v out ) is shorted to g nd. q1 r application circuits
ncp561 http://onsemi.com 9 minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. inches mm 0.028 0.7 0.074 1.9 0.037 0.95 0.037 0.95 0.094 2.4 0.039 1.0 tsop5 (footprint compatible with sot235)
ncp561 http://onsemi.com 10 ordering information device nominal output voltage marking package shipping ncp561sn15t1 1.5 lda ncp561sn18t1 1.8 lev ncp561sn25t1 2.5 ldc ncp561sn27t1 2.7 lex tsop5 3000 units/ ncp561sn28t1 2.8 ldd tsop 5 3000 units/ 7 tape & reel ncp561sn30t1 3.0 lde 7 ta e & reel ncp561sn33t1 3.3 ldf ncp561sn50t1 5.0 ldh additional voltages are available upon request by contacting your on semiconductor representative.
ncp561 http://onsemi.com 11 package dimensions tsop5 (sot235, sc595) sn suffix plastic package case 48301 issue b notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. dim min max min max inches millimeters a 2.90 3.10 0.1142 0.1220 b 1.30 1.70 0.0512 0.0669 c 0.90 1.10 0.0354 0.0433 d 0.25 0.50 0.0098 0.0197 g 0.85 1.05 0.0335 0.0413 h 0.013 0.100 0.0005 0.0040 j 0.10 0.26 0.0040 0.0102 k 0.20 0.60 0.0079 0.0236 l 1.25 1.55 0.0493 0.0610 m 0 10 0 10 s 2.50 3.00 0.0985 0.1181 0.05 (0.002) 123 54 s a g l b d h c k m j
ncp561 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncp561/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

▲Up To Search▲

Price & Availability of NCP561-D

	To Download NCP561-D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .